The standardization has been in progress recently on the method for testing integrated circuit cores mounted on a system-on-chip, as exemplified by IEEE P1500: Core Wrapper Architecture.
According to this standard, scannable flip-flops called ‘Wrapper register’ are provided on the peripheries of the cores, this makes the access becomes feasible to the cores from the exterior of LSI by means of serial signal transfer capability of the Wrapper register.
There connected to the Wrapper register are WPI (Wrapper Parallel Input) led to the input, and WPO (Wrapper Parallel Output) led to the output of the core. They are each connected serially to the Wrapper register and make it feasible to either apply test (test signals) for scanning the status of core ports or input serial test signals from the exterior.
The origin on the side of serial input to the Wrapper register is called WSI (Wrapper Serial Input), while the terminal on the side of serial output is WSO (Wrapper Serial Output). These WSI and WSO are interconnected to further WSI and WSO, which are provided separately in another core, so that a series can be formed.
Instructions to Wrapper register concerning to scanning and test application are controlled by WSC (Wrapper Serial Control). The WSC may connect to a command register of Boundary-scan Testing: IEEE 1149.1, or have their own command registers (WIR: Wrapper Instruction Register) to be arranged between TDI (test data in) and TDO (test data out) of the Boundary-scan Testing.
The Wrapper register is capable of transiting to safe mode through the control by the WSC or WIR. In the safe mode, the scan register in the interior of WPI operates to latch a logical value, 1 or 0, regardless of the state of the exterior of the core, while WPO controls the state of core output to either Hi-z state or logical value 1,0 regardless of the state within the core. Namely, in the safe mode, the core is excluded from the effects of external logics; namely the core is brought into the state separated from the exterior.
The type of core to be applicable to the Core Wrapper Architecture is not necessarily limiting. For example, after hierarchically dividing logics into modules with respect to function, Wrapper registers may be provided to ports of thus formed modules. Alternatively, Wrapper registers may be allocated to each layout block formed by hierarchical layout.
(1) Difficulty of Voltage Drop in Large Scale Circuits During Scan Test
Voltage drops in semiconductor chips are caused in general by parasitic resistance of power source wiring and current flowing through the resistance.
The degree of voltage drop at an arbitrary point j, ‘ΔVj’, is obtained as the product of two quantities, one the cumulative total of the parasitic resistance of source wiring up to the point j, ‘Rj’, and the other the amount of current flowing through the point j, ‘Ij’;ΔVj=Ij×Rj  (1).
Namely, the greater the number of cells operating simultaneously, the larger becomes the amount of current flowing in an instance. As a result, the voltage drop increases accordingly.
In addition, the larger the size of chip, the longer becomes the length of source wiring, so that the resistance increases. (Layout techniques through the analysis of voltage drops including preventive features have been disclosed in Japanese Laid-Open Patent Applications No. 2002-56044, 10-242283 and 2002-203001.)
In the case of scan test where the currents flow into all scan flip-flops included in an LSI in synchronous with a scan clock, this results in an instantaneous voltage drop. Therefore, for IC chips of relatively large size, difficulties are encountered more often such as the occurrence of scan test malfunction caused by the voltage drop, for example.
The techniques for averting the noted difficulties have been published as follows; a plurality of scan clocks is prepared and the phase of the scan clocks is made asynchronous with each other by means of a multi-phase generator provided in an LSI.
As a result, the scan flip-flops included in LSI can be prevented from operating simultaneously (Tsung-Chu Huang et al, “A Token Scan Architecture for Low Power Testing”, p.660, Proc. International Test Conference 2001 IEEE, October 30, Baltimore Md., USA).
In this method, however, there still left unresolved is the mismatch of the phase of the plural scan clocks, this arises difficulty of another malfunction caused by clock skew.
In addition, the above publication has also proposed the technique. in which, by dividing the scan chain and providing scan clocks exclusively in each of the divided blocks, the number of scan flip-flops simultaneously operating during test scan can decrease. In this technique, however, the original advantage of parallel operation is impaired, thereby giving rise to prolonging test time.
(2) Difficulty of Metastable State Propagation in Asynchronous Circuits
In an LSI provided with a plurality of system clocks each having different rates, there is possibility of causing metastable state during data exchange among different clocks.
This metastable state is known to cause system delay and malfunction. As a previous method for positively preventing this difficulty, flip-flops have been provided to synchronize asynchronous signals on the signal reception side of the logic.
Accordingly, in the method of scan test on large scale integrated circuits and in the case where all scan flip-flops included in the circuits are operated in synchronous one another with scan clock, an instantaneous voltage drop and scan test malfunction may result. Although techniques for averting the difficulties have been disclosed as described earlier by providing multiple scan clocks to thereby properly shift the phase of the clock and avoid the voltage drop, here gives rise to difficulties of skew and concomitant malfunction.
It is therefore desirable in the present disclosure the scan test is carried out on each of the blocks in parallel unaffected by surrounding logics and the skew between blocks can be avoided. Furthermore, the difficulty of voltage drop is also prevented.
As also described earlier, the addition of flip-flops are disclosed to achieve the synchronization to thereby alleviate the occurrence of the metastable state. However, this technique may have several problems remained unsolved such as a required areal overhead, omission of needed flip-flop, and further examination of method for confirming the flip-flop.
It is also desirable, therefore, to prevent the occurrence of the metastable state by using Wrapper register provided on the peripheries of the cores (or block).
Furthermore, another difficulty of fault detection described earlier has to be considered, which is caused by the safe mode capability.
That is, the core in the safe mode is excluded from the effects of external logics, and brought into the state separated from the exterior. Since the core is fixed to the state held by the Wrapper register in the safe mode, it becomes difficult in fault detection with ATPG (Auto Test Pattern Generation) to carry out the fault detection on logics provided between the Wrapper register and FF (flip-flop) included in the block. This is also true for the fault detection with BIST (Built-In Self Test).
It is therefore desirable to avert the difficulty in fault detection, and to thereby improve detection rate in such detections.